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| Products: |
Devices:
- CPLDs
- Low-Cost FPGAs
- High-Density FPGAs
- Structured ASICs
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| Applications:(CPLDs-MAX® II) |
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Lowest-cost, single-chip, easy-to-use CPLD family
Altera introduces the MAX® II device family, the lowest-cost CPLDs ever. MAX II devices are based on a groundbreaking new CPLD architecture that delivers the lowest cost per I/O pin and the lowest power of any CPLD family. Featuring a low-power process technology, MAX II devices deliver half the cost, one-tenth the power, four times the density, and twice the performance of previous MAX devices.
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| Characteristics: (CPLDs-MAX® II) |
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- Lowest CPLD cost & power consumption
- Highest CPLD density & performance
- Instant-on, non-volatile
- User flash memory
- 1.8-V, 2.5-V & 3.3-V supply voltages
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| Specifications:(CPLDs-MAX® II) |
| MX II Backgrounder (PDF) |
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| Applications:(CPLDs-MAX®) |
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Low-cost CPLD for lower-complexity, low-density designs
Altera's 3.3-V MAX® 3000A devices are based on the Altera® MAX architecture and are cost-optimized for high-volume applications. Manufactured on an advanced 0.30-µm CMOS process, the electrically erasable programmable read-only memory (EEPROM)-based MAX 3000A family provides instant-on capability and offers densities from 32 to 512 macrocells. MAX 3000A devices support in-system programmability (ISP) and can be easily reconfigured in the field. Each MAX 3000A macrocell is individually configurable for either sequential or combinatorial logic operation.
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| Characteristics: (CPLDs-MAX®) |
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- Low to moderate density
- Instant-on, non-volatile
- 5-V I/O support
- Deterministic timing
- 2.5-V, 3.3-V or 5.0-V supply voltages
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| Specifications:(CPLDs-MAX®) |
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| Applications:(FPGA Conversion ULC Device/s-Cyclone II) |
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Second-generation, lowest-cost family in the CycloneT FPGA series for designs where cost concerns outweigh the need for performance or extensive features
Altera introduces the CycloneT II FPGA family, the latest in the Cyclone series of low-cost FPGAs. Altera forever changed the FPGA industry with the introduction of the Cyclone device family in 2002-bringing to market the first and only FPGA family designed from the ground up for the lowest cost. Altera took the same approach and built the Cyclone II family with each member individually optimized for minimum die size. The Cyclone II FPGA family offers the same benefits as its predecessor-a customer-defined feature set, industry-leading performance, and low power consumption-but with much more density and features-at dramatically lower costs. Cyclone II devices extend the low-cost FPGA density range up to 68,416 logic elements (LEs) and up to 1.1 Mbits of embedded memory.
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| Characteristics: (FPGA Conversion ULC Device/s-Cyclone II) |
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- Nios® II embedded processor support
- Embedded 18x18 digital signal processing (DSP) multipliers
- Moderate on-chip memory
- Moderate-speed I/O & memory interfaces
- Broad intellectual property (IP) portfolio support
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| Specifications:(FPGA Conversion ULC Device/s-Cyclone II) |
| Cyclone II Device Family Data Sheet |
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| Applications:(FPGA Conversion ULC Device/s-Cyclone) |
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First-generation, lower-density, low-cost family in the Cyclone FPGA series
Altera's CycloneT series of FPGAs provides the benefits of programmable logic at price points competitive with ASICs and ASSPs. Built from the ground up based on extensive input from hundreds of customers, these low-cost devices provide high-volume, application-focused features such as embedded memory, external memory interfaces, and clock management circuitry. Cyclone series FPGAs are the optimal solution for high-volume, price-sensitive applications that previously required the use of fixed solutions such as gate arrays and standard cells.
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| Characteristics: (FPGA Conversion ULC Device/s-Cyclone) |
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- Nios II embedded processor support
- Low to moderate on-chip memory
- Low to moderate-speed I/O & memory interfaces
- Broad IP portfolio support
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| Specifications:(FPGA Conversion ULC Device/s-Cyclone) |
| Cyclone Device Family Data Sheet |
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