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Home > Logic ICs > Flip Flops > 74LS74ADP-51A Mitsubishi Dual Positive-Edge-Triggered D Flip-Flop

74LS74ADP-51A Mitsubishi Dual Positive-Edge-Triggered D Flip-Flop

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Quick Overview

74LS74A DP-51A Mitsubishi Dual Positive-Edge-Triggered D Flip-Flop

74LS74ADP-51A Mitsubishi Dual Positive-Edge-Triggered D Flip-Flop

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Details

74LS74ADP-51A Mitsubishi Dual Positive-Edge-Triggered D Flip-Flop with Preset, Clear and Complementary Outputs

This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.

Additional Information

M74LS74ADP-51A
Click here to Download Datasheet I
Click here to Download Datasheet II
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