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Home > Semiconductors > ICs > Interface ICs > Memory > CY7C199L-15VC CYPRESS SRAM Chip Async Single 5V 256K-Bit

CY7C199L-15VC CYPRESS SRAM Chip Async Single 5V 256K-Bit

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Cypress - Cypress Cy7C199L-15Vc IC SRAM Chip Async Single 5V 256K-Bit 32K x 8 15ns 28-Pin Molded SOJ

CY7C199L-15VC CYPRESS SRAM Chip Async Single 5V 256K-Bit

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CYPRESS CY7C199L-15VC SRAM Chip Async Single 5V 256K-Bit 32K x 8 15ns 28-Pin Molded SOJ

Features

· High speed 10 ns· Fast tDOE· CMOS for optimum speed/power· Low active power 467 mW (max, 12 ns "L" version)· Low standby power 0.275 mW (max, "L" version)· 2V data retention ("L" version only)· Easy memory expansion with CE and OE features· TTL-compatible inputs and outputs· Automatic power-down when deselected is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and three-state drivers. This device has an automatic power-down feature, reducing the power consumption by 81% when deselected. The is in the standard 300-mil-wide DIP, SOJ, and LCC packages. An active LOW Write Enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and Write Enable (WE) is HIGH. A die coat is used to improve alpha immunity.

Additional Information

CY7C199L-15VC
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