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Home > Interface ICs > Programmable Logic ICs > CY7B992-7JC Cypress IC Zero Delay Programmable PLL Clock Buffer Single 15MHz to 80MHz 32-Pin PLCC

CY7B992-7JC Cypress IC Zero Delay Programmable PLL Clock Buffer Single 15MHz to 80MHz 32-Pin PLCC

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Cypress - Cypress Cy7B992-7Jc IC Zero Delay Programmable PLL Clock Buffer Single 15MHz to 80MHz 32-Pin PLCC

CY7B992-7JC Cypress IC Zero Delay Programmable PLL Clock Buffer Single 15MHz to 80MHz 32-Pin PLCC

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CYPRESS - CYPRESS CY7B992-7JC Zero Delay Programmable PLL Clock Buffer Single 15MHz to 80MHz 32-Pin PLCC

500-ps max. Total Timing BudgetTM (TTBTM) window· 24­200-MHz (CY7B994V) input/output operation· Matched pair output skew < 200 ps· Zero input-to-output delay· 18 LVTTL outputs driving 50 terminated lines· 16 outputs at 200 MHz: Commercial temperature· 6 outputs at 200 MHz: Industrial temperature· 3.3V LVTTL/LVPECL, fault-tolerant, and hot insertable reference inputs· Phase adjustments in 625-/1300-ps steps ± 10.4 ns· Multiply/divide ratios of Individual output bank disable· Output high-impedance option for testing purposes· Fully integrated phase-locked loop (PLL) with lock indicator· <50-ps typical cycle-to-cycle jitter· Single ± 10% supply· 100-pin TQFP package· 100-lead BGA package

The CY7B993V and CY7B994V High-speed Multi-phase PLL Clock Buffers offer user-selectable control over system clock functions. This multiple-output clock driver provides the system integrator with functions necessary to optimize the timing of high-performance computer and communication systems. These devices feature a guaranteed maximum TTB window specifying all occurrences of output clocks with respect to the input reference clock across variations in output frequency, supply voltage, operating temperature, input edge rate, and process. Eighteen configurable outputs each drive terminated transmission lines with impedances as low as 50 while delivering minimal and specified output skews at LVTTL levels. The outputs are arranged in five banks. Banks 4 of four outputs allow a divide function to 12, while simultaneously allowing phase adjustments in 625­1300-ps increments to 10.4 ns. One of the output banks also includes an independent clock invert function. The feedback bank consists of two outputs, which allows divide-by functionality from to 12 and limited phase adjustments. Any one of these eighteen outputs can be connected to the feedback input as well as driving other inputs. Selectable reference input is a fault tolerance feature that allows smooth change-over to secondary clock source, when the primary clock source is not in operation. The reference inputs and feedback inputs are configurable to accommodate both LVTTL or Differential (LVPECL) inputs. The completely integrated PLL reduces jitter and simplifies board layout.

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CY7B992-7JC
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