Country Flags IBS Electronics USA IBS Electronics Mexico IBS Electronics Philippines IBS Electronics China IBS Electronics Malaysia IBS Electronics India IBS Electronics Hong Kong IBS Electronics Singapore
Home > DRAM > Hynix HY57V161610DTC-7 CMOS Synchronous DRAM 16,777,216-bits

Hynix HY57V161610DTC-7 CMOS Synchronous DRAM 16,777,216-bits

Be the first to review this product

Availability: In stock

Only 55 left

$5.2700
OR

Quick Overview

Hynix - Hynix Hy57V161610Dtc-7 IC THE Hyundai HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic applications which require large memory density and high bandwidth. HY57V161610D is organized as 2banks of 524,288x16. HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipeline design is not restricted by a `2N` rule.)
FEATURES
· · · · · · Single 3.0V to 3.6V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM/LDQM Internal two banks operation · · · · Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 and Full Page for Sequence Burst - 1, 2, 4 and 8 for Interleave Burst Programmable CAS Latency ; 1, 2, 3 Clocks

Hynix HY57V161610DTC-7 CMOS Synchronous DRAM 16,777,216-bits

Double click on above image to view full picture

Zoom Out
Zoom In

More Views

Details

HY57V161610DTC-7 Hynix DRAM 16777216-bits CMOS Synchronous

Hynix - Hy57V161610Dtc-7 The Hynix HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic applications which require large memory density and high bandwidth. HY57V161610D is organized as 2banks of 524,288x16. HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipeline design is not restricted by a `2N` rule.)
FEATURES
· · · · · · Single 3.0V to 3.6V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM/LDQM Internal two banks operation · · · · Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 and Full Page for Sequence Burst - 1, 2, 4 and 8 for Interleave Burst Programmable CAS Latency ; 1, 2, 3 Clocks

Additional Information

HY57V161610DTC-7
Click here to Download Datasheet I
© 1994 - 2019 IBS Electronics Inc. All rights Reserved.    •    Call Now: 1-800-717-6475     Go to Top  Go to Top of Page