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ICS AV9173-01CS08 Video Genlock PLL SMD SOIC-8

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ICS AV9173-01CS08 Video Genlock PLL SMD SOIC-8

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ICS AV9173-01CS08 Video Genlock PLL SMD SOIC-8

The AV9173-01 provides the analog circuit blocks required for implementing a video genlock dot (pixel) clock generator. It contains a phase detector, charge pump, loop filter, and voltage-controlled oscillator (VCO). By grouping these critical analog blocks into one IC and utilizing external digital functions, performance and design flexibility are optimized as are development time and system cost.

The AV9173-01 provides the analog circuit blocks required for implementing a video genlock dot (pixel) clock generator. It contains a phase detector, charge pump, loop filter, and voltage-controlled oscillator (VCO). By grouping these critical analog blocks into one IC and utilizing external digital functions, performance and design flexibility are optimized as are development time and system cost. When used with an external clock divider, the AV9173-01 forms a Phase-Locked Loop configured as a frequency synthesizer. The AV9173-01 is designed to accept video horizontal synchronization (h-sync) pulses and produce a video dot clock. A separated, negative-going sync input reference pulse is required at pin 2 (I N). The AV9173-01 is also suited for other clock recovery applications in such areas as data communications.

Features

Phase-detector/VCO circuit block Ideal for genlock system Reference clock range 25 kHz to 1 MHz for full output clock range Input clocks down to 12 kHz possible with restricted output conditions (see Table 1) Output clock range to 75MHz On-chip loop filter Single 5 volt power supply Low power CMOS technology Small 8-pin DIP or SOIC package

ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

PIN NUMBER PIN NAME FBIN IN GND OE CLK1 VDD CLK2 TYPE Input Output DESCRIPTION Feedback Input for reference sync pulse Ground Frequency Select 0 input Output Enable Clock Output 1 Power Supply (+5V) Clock Output 2 (Divided-by-2 from Clock 1)

Table 1: Allowable Input Frequency to Output Frequency (Outputs in MHz)

Most video sources, such as video cameras, are asynchronous, free-running devices. To digitize video or synchronize one video source to another free-running reference video source, a video "genlock" (generator lock) circuit is required. The AV9173-01 integrates the analog blocks which make the task much easier. In the complete video genlock circuit, the primary function of the is to provide the analog circuitry required to generate the video dot clock within a PLL. This application is illustrated in Figure 1. The input reference signal for this circuit is the horizontal synchronization (h-sync) signal. If a composite video reference source is being used, the h-sync pulses must be separated from the composite signal. A video sync separator circuit, such as the National Semiconductor LM1881, can be used for this purpose. The clock feedback divider shown in Figure is a digital divider used within the PLL to multiply the reference frequency. Its divide ratio establishes how many video dot clock cycles occur per h-sync pulse. For example, if 880 pixel clocks are desired per h-sync pulse, then the divider ratio is set to 880. Hence, together the h-sync frequency and external divider ratio establish the dot clock frequency: AC specifications (VCO frequency), an input as low as 12kHz (such as NTSC or PAL h-sync) can be used. The output hook-up of the AV9173-01 is dictated by the desired dot clock frequency. The primary consideration is the internal VCO which operates over a frequency range of 10 MHz to 75 MHz. Because of the selectable VCO output divider and the additional divider on output CLK2, four distinct output frequency ranges can be achieved. The following Table lists these ranges and the corresponding device configuration.

Note that both outputs, CLK1 and CLK2, are available during operation even though only one is fed back via the external clock divider. Pin 5, OE, tristates both CLK1 and CLK2 upon logic low input. This feature can be used to revert dot clock control to the system clock when not in genlock mode (hence, when in genlock mode the system dot clock must be tristated). When unused, inputs FS0 and OE must be tied to either GND (logic low) or VDD (logic high). For further discussion of VCO/PLL operation as it applies to the AV9173-01, please refer to the AV9170 application note. The is a similar device with fixed feedback dividers for skew control applications.

Both AV9173-01 input pins IN and FBIN respond only to negative-going clock edges of the input signal. The h-sync signal must be constant frequency in the 25 kHz to 1 MHz range and stable (low clock jitter) for creation of a stable output clock. Refer to Application Brief (AB01) for additional details on use of input frequencies below 25kHz. By following the guidelines in this brief and meeting the test conditions in the

Additional Information

AV9173-01C508
Click here to Download Datasheet I
Click here to Download Datasheet II
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