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MOTOROLA SN74LS122DR2 Monostable Multivibrator Single

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Motorola - Mot Sn74Ls122Dr2 Monostable Multivibrator Single 14-Pin SOIC

MOTOROLA SN74LS122DR2 Monostable Multivibrator Single

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MOTOROLA SN74LS122DR2 Monostable Multivibrator Single 14-Pin SOIC

Reset Trigger Monostable Multivibrator, Package: Soic, Pins=14



Part #: SN74LS122DR2
Part Category: Logic ICs
Description: LS SERIES, MONOSTABLE MULTIVIBRATOR, PDSO14
Package Description PLASTIC, SOIC-14
REACH Compliant Yes
Status Discontinued
Logic IC Type MONOSTABLE MULTIVIBRATOR
Sub Category Prescaler/Multivibrators
Family LS
JESD-30 Code R-PDSO-G14
JESD-609 Code e0
Number of Data/Clock Inputs 4
Number of Functions 1
Motorola - Sn74Ls122Dr2 Monostable Multivibrator Single 14-Pin SOIC


Features, Applications

These dc triggered multivibrators feature pulse width control by three methods. The basic pulse width is programmed by selection of external resistance and capacitance values. The LS122 has an internal timing resistor that allows the circuits to be used with only an external capacitor. Once triggered, the basic pulse width may be extended by retriggering the gated low-level-active (A) or high-level-active (B) inputs, or be reduced by use of the overriding clear.· Overriding Clear Terminates Output Pulse· Compensated for VCC and Temperature Variations· DC Triggered from Active-High or Active-Low Gated Logic Inputs· Retriggerable for Very Long Output Pulses, to 100% Duty Cycle· Internal Timing Resistors on LS122

Symbol VCC TA IOH IOL Rext Cext Rext/Cext Parameter Supply Voltage Operating Ambient Temperature Range Output Current ­ High Output Current ­ Low External Timing Resistance External Capacitance Wiring Capacitance at Rext/Cext Terminal 5.0 Min 4.75 0 Typ 5.0 25 Max No Restriction 50 pF

Device SN74LS123M SN74LS123MEL Package 14 Pin DIP SOIC­14 16 Pin DIP SOIC­16 SOEIAJ­16 Shipping 2000 Units/Box 55 Units/Rail 2500/Tape & Reel 2000 Units/Box 38 Units/Rail 2500/Tape & Reel See Note 1 See Note 1

1. For ordering information on the EIAJ version of the SOIC package, please contact your local ON Semiconductor representative.

NOTES: 1. An external timing capacitor may be connected between Cext and Rext/Cext (positive). 2. To use the internal timing resistor of the LS122, connect Rint to VCC. 3. For improved pulse width accuracy connect an external resistor between Rext/Cext and VCC with Rint opencircuited. 4. To obtain variable pulse widths, connect an external variable resistance between Rint/Cext and VCC.

TYPICAL APPLICATION DATA The output pulse is a function of the external components, Cext and Rext or Cext and Rint on the LS122. For values of Cext 1000 pF, the output pulse at VCC 5.0 V and VRC 5.0 V (see Figures 1, 2, and 3) is given = K Rext Cext where K is nominally 0.45 If Cext on pF and Rext in k then is in nanoseconds. The Cext terminal of the LS122 and is an internal connection to ground, however for the best system performance Cext should be hard-wired to ground. Care should be taken to keep Rext and Cext as close to the monostable as possible with a minimum amount of inductance between the Rext/Cext junction and the Rext/Cext pin. Good groundplane and adequate bypassing should be designed into the system for optimum performance to ensure that no false triggering occurs. It should be noted that the Cext pin is internally connected to ground on the LS122 and LS123, but not on the LS221. Therefore, if Cext is hard-wired externally to ground, substitution a LS221 onto a LS123 socket will cause the LS221 to become non-functional. The switching diode is not needed for electrolytic capacitance application and should not be used on the LS122 and LS123. To find the value of K for Cext 1000 pF, refer to Figure 4. Variations on VCC or VRC can cause the value K to change, as can the temperature of the LS123, LS122.

Figures 5 and 6 show the behavior of the circuit shown in Figures 1 and 2 if separate power supplies are used for VCC and VRC. If VCC is tied to VRC, Figure 7 shows how K will vary with VCC and temperature. Remember, the changes in Rext and Cext with temperature are not calculated and included in the graph. As long as Cext 1000 pF and 5K Rext 260K, the change in K with respect to Rext is negligible. If Cext 1000 pF the graph shown on Figure 8 can be used to determine the output pulse width. Figure 9 shows how K will change for Cext pF if VCC and VRC are connected to the same power supply. The pulse width tW in nanoseconds is approximated by tW Cext (pF) + 0.45 Rext (k) Cext + 11.6 Rext In order to trim the output pulse width, it is necessary to include a variable resistor between VCC and the Rext/Cext pin or between VCC and the Rext pin of the LS122. Figure 10, 11, and 12 show how this can be done. Rext remote should be kept as close to the monostable as possible. Retriggering of the part, as shown in Figure 3, must not occur before Cext is discharged or the retrigger pulse will not have any effect. The discharge time of Cext in nanoseconds is guaranteed to be less than 0.22 Cext (pF) and is typically 0.05 Cext (pF). For the smallest possible deviation in output pulse widths from various devices, it is suggested that Cext be kept 1000 pF.

Additional Information

SN74LS122DR2
Click here to Download Datasheet I
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