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Home > Semiconductors > ICs > Logic ICs > Counter Shift Registers > Philips 74HC93D IC 4-bit Binary Ripple Counter 100MHZ, SOIC-14

Philips 74HC93D IC 4-bit Binary Ripple Counter 100MHZ, SOIC-14

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Quick Overview

Philips 74Hc93D Smd IC Counter IC Binary Counter 1 Element 4 Bit Negative Edge 100MHZ 14-SO

Philips 74HC93D IC 4-bit Binary Ripple Counter 100MHZ, SOIC-14

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Philips / NXP Semiconductors 74HC93D IC Counter/Divider Single 4-Bit Binary UP 14-Pin SO T/R

·The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications· The IC06 74HC/HCT/HCU/HCMOS Logic Package Information· The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

The 74HC/HCT93 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT93 are 4-bit binary ripple counters. The devices consist of four master-slave flip-flops internally connected to provide a divide-by-two section and a divide-by-eight section. Each section has a separate clock input (CP 0 and CP 1) to initiate state changes of the counter on the HIGH-to-LOW clock transition. State changes of the Qn outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes.

A gated AND asynchronous master reset (MR1 and MR2) is provided which overrides both clocks and resets (clears) all flip-flops.

Since the output from the divide-by-two section is not internally connected to the succeeding stages, the device may be operated in various counting modes. In a 4-bit ripple counter the output Q0 must be connected externally to input CP 1. The input count pulses are applied to clock input CP 0. Simultaneous frequency divisions of 2, 4, 8 and 16 are performed at the Q0, Q1, Q2 and Q3 outputs as shown in the function table. As a 3-bit ripple counter the input count pulses are applied to input CP 1.

Simultaneous frequency divisions of 2, 4 and 8 are available at the Q1, Q2 and Q3 outputs. Independent use of the first flip-flop is available if the reset function coincides with reset of the 3-bit ripple-through counter.

The 74HC93D is a 4-bit binary Ripple Counter pin compatible with low power Schottky TTL (LSTTL). It consists of four master-slave flip-flops internally connected to provide a divide-by-two section and a divide-by-eight section. Each section has a separate clock input (CP0\ and CP1\) to initiate state changes of the counter on the high-to-low clock transition. State changes of the Qn outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. A gated AND asynchronous master reset (MR1 and MR2) is provided which overrides both clocks and resets (clears) all flip-flops. Since the output from the divide-by-two section is not internally connected to the succeeding stages, the device may be operated in various counting modes. In a 4-bit ripple counter the output Q0 must be connected externally to input CP1\.
  • Various counting modes
  • Asynchronous master reset
  • ICC Category
  • Standard output capability
  • Complies with JEDEC standard No. 7A

Applications

Industrial, Consumer Electronics, Computers & Computer Peripherals

Additional Information

74HC93D
Manufacturer: NXP
Product Category: Counter ICs
Brand: NXP Semiconductors
Counter Type: Binary
Logic Family: 74HC
Number of Bits: 4
Counting Method: Synchronous/Asynchronous
Counting Sequence: Up/Down
Operating Supply Voltage: 2 V to 6 V
Operating Temperature Range: - 40 C to + 85 C
Mounting Style: SMD/SMT
Package / Case: SO-14
Click here to Download Datasheet I
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