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Home > Logic ICs > Flip Flops > Signetics 74LS112D Dual Negative Edge Trigger J-K Flip Flop DIP-16

Signetics 74LS112D Dual Negative Edge Trigger J-K Flip Flop DIP-16

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Sig - Sig 74Ls112D IC

Signetics 74LS112D Dual Negative Edge Trigger J-K Flip Flop DIP-16

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Signetics 74LS112D Dual Negative Edge Trigger J-K Flip Flop DIP-16

The SN54/74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up and hold time are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.

This device contains two independent negative-edge-trig- gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the falling edge of the clock pulse. Data on the J and K inputs may be changed while the clock is HIGH or LOW without affecting the outputs as long as the setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs

Additional Information

74LS112N
Manufacturer: Signetics (Acquired by Philips)
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