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Home > Semiconductors > ICs > TI SN74ALS112AN 74ALS112AN IC Dual Neg-Edge-Trig DIP16

TI SN74ALS112AN 74ALS112AN IC Dual Neg-Edge-Trig DIP16

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TI - TI SN74ALS112AN 74ALS112 AN DIP Dual Neg-Edge-Trig J-K Flip-Flop

TI SN74ALS112AN 74ALS112AN IC Dual Neg-Edge-Trig DIP16

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TI - 74ALS112AN Dual J-K negative edge-triggered flip-flopDual Neg-Edge-Trig J-K Flip-Flop




Mfr Package Description ROHS COMPLIANT,PLASTIC, DIP-16
REACH Compliant Yes
EU RoHS Compliant Yes
China RoHS Compliant Yes
Status Active
Sub Category FF/Latches
Family ALS
fmax-Min 30.0 MHz
JESD-30 Code R-PDIP-T16

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE ) or clear (CLR ) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock p ulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

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