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MOTOROLA 74HC373N IC LATCH 6V OCTAL D 3STATE 20DIP

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74HC373N MOTOROLA D-Type Transparent Latch Channel 8:8 IC Tri-State 20-DIP

MOTOROLA 74HC373N IC LATCH 6V OCTAL D 3STATE 20DIP

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MOTOROLA 74HC373N IC LATCH TRANSP OCTAL D 3STATE 20DIP

Description

  • Latch Logic IC
  • Latch Type:D Type Transparent
  • Output Current:35mA
  • Propagation Delay:12ns
  • Output Type:Tri State
  • Supply Voltage Range:2V to 6V
  • Logic Case Style:DIP
  • No. of Pins:20
  • Operating Temperature Range:-40°C to +125°C
  • RoHS Compliant: Yes

The 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.

The 74HC373; 74HCT373 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all latches.

The 74HC373; 74HCT373 consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D input changes.

When LE is LOW the latches store the information that was present at the D inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the highimpedance OFF-state. Operation of the OE input does not affect the state of the latches.

The 74HC373; 74HCT373 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.


The 74HC373N is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.

The 74HC373 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all latches.

Features:

3-state non-inverting outputs for bus oriented applications
Common 3-state output enable input
Functionally identical to the 74HC563; 74HCT563 and 74HC573; 74HCT573
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Specified from –40 ? to +85 ? and from –40 ? to +125 ?
Status: Transfered 74HC373N to Freescale Semiconductor

Additional Information

74HC373N
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