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SYBERGY SY100S838ZC IC CLOCK GEN 3.3V/5V

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SYBERGY SY100S838ZC IC CLOCK GEN 3.3V/5V

SYBERGY SY100S838ZC IC CLOCK GEN 3.3V/5V

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SYBERGY SY100S838ZC IC CLOCK GEN 3.3V/5V

FEATURES

3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75K input pull-down resistors Available in 20-pin SOIC package

DESCRIPTION

The is a low skew ÷4/ 6) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be ACcoupled into the device. If a single-ended input to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The V BB output is designed to act as the switching reference for the input of the SY100S838/L under singleended input conditions. As a result, this pin can only source/sink 0.5mA of current. The Function Select (FSEL) input is used to determine what clock generation chip function is. When FSEL input is LOW, SY100S838/L functions as a divide by 2 and by 4/6 clock generation chip. However, if FSEL input is HIGH, it functions as a divide by 1 and by 2/3 clock chip. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as for multiple in a system.

Specifications  
Type Clock Generator
PLL No
Input ECL, PECL
Output Clock
Frequency - Max 1GHz
Number of Circuits 1
Ratio - Input Output 1 4
Differential - Input Output Yes/Yes
Divider/Multiplier Yes/No
Voltage - Supply 4.2 V ~ 5.5 V
Operating Temperature 0°C ~ 85°C
Mounting Type Surface Mount
Package / Case 20-SOIC (0.295", 7.50mm Width)
Packaging Tube
Supplier Device Package 20-SOIC (Wide)
Lead Free Status Contains Lead
RoHS Status RoHS Non-Compliant

Additional Information

SY100S838ZC
Click here to Download Datasheet I
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