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XC17512LPC20I XILINX IC PROM SER I-TEMP 512K 20-PLCC

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Xilinx Technologies XC17512LPC20I Memory 512kb 3V -3.6 V

XC17512LPC20I XILINX IC PROM SER I-TEMP 512K 20-PLCC

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Xilinx Technologies Inc XC17512LPC20I Memory - Configuration Prom For Fpgas' Integrated Circuit (ics) OTP Tube 3 V ~ 3.6 V
^Specifications
^Programmable Type OTP
^Memory Size 512kb
^Package / Case 20-LCC (J-Lead)
^Packaging Tube
^Voltage - Supply 3 V ~ 3.6 V
^Operating Temperature 0C ~ 70C
^Lead Free Status Contains Lead
^RoHS Status RoHS Non-Compliant
^
^The XC1700 family of configuration PROMs provides an easy-to-use, cost-effective method for storing large Xilinx FPGA configuration bitstreams. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal. Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family. For device programming, either the Xilinx Alliance or Foundation series development system compiles the FPGA design file into a standard Hex format, which is then transferred to most commercial PROM programmers.

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XC17512LPC20I
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