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Home > DRAM > Hynix HY57V161610DTC-7 Synchronous DRAM, 1MX16, 5.5ns, CMOS, PDSO50

Hynix HY57V161610DTC-7 Synchronous DRAM, 1MX16, 5.5ns, CMOS, PDSO50

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Hynix HY57V161610DTC-7 Hyundai 16,777,216-bits CMOS 2 Banks X 512K X 16 Bit Synchronous DRAM PDSO50

Hynix HY57V161610DTC-7 Synchronous DRAM, 1MX16, 5.5ns, CMOS, PDSO50

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HY57V161610DTC-7 Hynix DRAM 16777216-bits CMOS Synchronous 1MX16, 5.5ns, CMOS, PDSO50
SPECIFICATIONS

Mfr Package Description 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50
Status Discontinued
Sub Category DRAMs
Access Mode DUAL BANK PAGE BURST
Access Time-Max 5.5 ns

Hynix - Hy57V161610Dtc-7 The Hynix HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic applications which require large memory density and high bandwidth. HY57V161610D is organized as 2banks of 524,288x16. HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipeline design is not restricted by a `2N` rule.)
FEATURES
· · · · · · Single 3.0V to 3.6V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM/LDQM Internal two banks operation · · · · Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 and Full Page for Sequence Burst - 1, 2, 4 and 8 for Interleave Burst Programmable CAS Latency ; 1, 2, 3 Clocks


The SK Hynix HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphicapplications which require large memory density and high bandwidth. HY57V161610D is organized as 2banks of 524,288x16.
HY57V161610D is offering fully synchronous operation referenced to a positive edge clock.
All inputs and outputs are synchronizedwith the rising edge of the clock input.
The data paths are internally pipelined to achieve very high bandwidth. All input and outputvoltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave).
Aburst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by anew burst read or write command on any cycle. (This pipeline design is not restricted by a `2N` rule.)
Features
Single 3.0V to 3.6V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin pitch
All inputs and outputs referenced to positive edge of system clock
Data mask function by UDQM/LDQM
Internal two banks operation
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
1, 2, 4, 8 and Full Page for Sequence Burst
1, 2, 4 and 8 for Interleave Burst
Programmable CAS Latency ; 1, 2, 3 Clocks

Additional Information

HY57V161610DTC-7
Click here to Download Datasheet I
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